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72-mbit (2m x 36/4m x 18/1m x 72) flow-through sram cy7c1481v33 cy7c1483v33 cy7c1487v33 cypress semiconductor corporation ? 198 champion court ? san jose , ca 95134-1709 ? 408-943-2600 document #: 38-05284 rev. *h revised may 01, 2007 features ? supports 133 mhz bus operations ? 2m x 36/4m x 18/1m x 72 common io ? 3.3v core power supply (v dd ) ? 2.5v or 3.3v i/o supply (v ddq ) ? fast clock-to-output times ? 6.5 ns (133 mhz version) ? provide high-performance 2-1-1-1 access rate ? user selectable burst counter supporting intel ? pentium ? interleaved or linear burst sequences ? separate processor and controller address strobes ? synchronous self timed write ? asynchronous output enable ? cy7c1481v33, cy7c1483v33 available in jedec-standard pb-free 100-pin tqfp, pb-free and non-pb-free 165-ball fbga package. cy7c1487v33 available in pb-free and non-pb-free 209 ball fbga package ? ieee 1149.1 jtag-compatible boundary scan ? ?zz? sleep mode option functional description [1] the cy7c1481v33/cy7c1483v33/cy7c1487v33 is a 3.3v, 2m x 36/4m x 18/1m x 72 synchronous flow-through sram designed to interface with high speed microprocessors with minimum glue logic. maximum a ccess delay from clock rise is 6.5 ns (133 mhz version). a two-bit on-chip counter captures the first address in a burst and increments the address automatically for the rest of the burst access. all synchronous inputs are gated by registers controlled by a positive-edge-triggered clock input (clk). the synchronous inputs include all addresses, all data inputs, address-pipelining chip enable (ce 1 ), depth-expansion chip enables (ce 2 and ce 3 ), burst control inputs (adsc , adsp , and adv ), write enables (bw x and bwe ), and global write (gw ). asynchronous inputs include the output enable (oe ) and the zz pin. the cy7c1481v33/cy7c1483v33/cy7c1487v33 allows either interleaved or linear burst sequences, selected by the mode input pin. a high selects an interleaved burst sequence, while a low selects a linear burst sequence. burst accesses can be initiated with the processor address strobe (adsp ) or the cache controller address strobe (adsc ) inputs. address advancement is controlled by the address advancement (adv ) input. addresses and chip enables are registered at rising edge of clock when either address strobe processor (adsp ) or address strobe controller ( adsc ) are active. subsequent burst addresses can be internally generated as controlled by the advance pin (adv ). the cy7c1481v33/cy7c1483v33/cy7c1487v33 operates from a +3.3v core power supply while all outputs may operate with either a +2.5 or +3.3v supply. all inputs and outputs are jedec standard jesd8-5 compatible. selection guide 133 mhz 100 mhz unit maximum access time 6.5 8.5 ns maximum operating current 335 305 ma maximum cmos standby current 150 150 ma note 1. for best practices recommendations, refer to the cypress application note an1064, sram system guidelines . [+] feedback [+] feedback
cy7c1481v33 cy7c1483v33 cy7c1487v33 document #: 38-05284 rev. *h page 2 of 30 logic block diagram ? cy7c1481v33 (2m x 36) address register burst counter and logic clr q1 q0 enable register sense amps output buffers input registers memory array mode a [1:0] zz dq s dqp a dqp b dqp c dqp d a 0, a1, a adv clk adsp adsc bw d bw c bw b bw a bwe ce1 ce2 ce3 oe gw sleep control dq a , dqp a byte write register dq b , dqp b byte write register dq c , dqp c byte write register byte write register dq d , dqp d byte write register dq d , dqp d byte write register dq c , dqp c byte write register dq b , dqp b byte write register dq a , dqp a byte write register logic block diagram ? cy7c1483v33 (4m x 18) address register adv clk burst counter and logic clr q1 q0 adsc ce 1 oe sense amps memory array adsp output buffers input registers mode ce 2 ce 3 gw bwe a 0,a1,a bw b bw a dq b ,dqp b write register dq a ,dqp a write register enable register a[1:0] dqs dqp a dqp b dq b ,dqp b write driver dq a ,dqp a write driver sleep control zz [+] feedback [+] feedback
cy7c1481v33 cy7c1483v33 cy7c1487v33 document #: 38-05284 rev. *h page 3 of 30 logic block diagram ? cy7c1487v33 (1m x 72) bw d bw c bw b bw a bwe gw ce1 ce2 ce3 oe enable register pipelined enable address register adv clk binary counter clr q1 q0 adsp adsc mode a 0, a1,a a[1:0] bw f bw e bw h bw g dqs dqp a dqp b dqp c dqp d dqp e dqp f dqp g dqp h output registers memory array output buffers e dq a , dqp a write driver dq b , dqp b write driver dq c , dqp c write driver dq d , dqp d write driver input registers byte a write driver dq e , dqp e write driver dq f , dqp f write driver dq g , dqp g write driver dq h , dqp h write driver sense amps sleep control zz dq a , dqp a write driver dq b , dqp b write driver dq c , dqp c write driver dq d , dqp d write driver dq e , dqp e write driver dq f , dqp f write driver dq f , dqp f write driver dq h , dqp h write driver [+] feedback [+] feedback
cy7c1481v33 cy7c1483v33 cy7c1487v33 document #: 38-05284 rev. *h page 4 of 30 pin configurations a a a a a 1 a 0 a a v ss v dd a a a a a a a a dqp b dq b dq b v ddq v ssq dq b dq b dq b dq b v ssq v ddq dq b dq b v ss nc v dd zz dq a dq a v ddq v ssq dq a dq a dq a dq a v ssq v ddq dq a dq a dqp a dqp c dq c dq c v ddq v ssq dq c dq c dq c dq c v ssq v ddq dq c dq c v dd nc v ss dq d dq d v ddq v ssq dq d dq d dq d dq d v ssq v ddq dq d dq d dqp d a a ce 1 ce 2 bw d bw c bw b bw a ce 3 v dd v ss clk gw bwe oe adsc adsp adv a a 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51 100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 mode cy7c1481v33 (2mx 36) nc a a a a a 1 a 0 a a v ss v dd a a a a a a a a a nc nc v ddq v ssq nc dqp a dq a dq a v ssq v ddq dq a dq a v ss nc v dd zz dq a dq a v ddq v ssq dq a dq a nc nc v ssq v ddq nc nc nc nc nc nc v ddq v ssq nc nc dq b dq b v ssq v ddq dq b dq b v dd nc v ss dq b dq b v ddq v ssq dq b dq b dqp b nc v ssq v ddq nc nc nc a a ce 1 ce 2 nc nc bw b bw a ce 3 v dd v ss clk gw bwe oe adsc adsp adv a a 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51 100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 mode cy7c1483v33 (4m x 18) nc a a 100-pin tqfp pinout [+] feedback [+] feedback
cy7c1481v33 cy7c1483v33 cy7c1487v33 document #: 38-05284 rev. *h page 5 of 30 pin configurations (continued) 165-ball fbga (15 x 17 x 1.4 mm) pinout cy7c1481v33 (2m x 36) cy7c1483v33 (4m x 18) 234 567 1 a b c d e f g h j k l m n p r tdo nc/288m nc/144m dqp c dq c dqp d nc dq d ce 1 bw b ce 3 bw c bwe a ce 2 dq c dq d dq d mode nc dq c dq c dq d dq d dq d a a v ddq bw d bw a clk gw v ss v ss v ss v ss v ddq v ss v dd v ss v ss v ss v ss v ss v ss v ddq v ddq nc v ddq v ddq v ddq v ddq a a v dd v ss v dd v ss v ss v ddq v dd v ss v dd v ss v dd v ss v ss v ss v dd v dd v ss v dd v ss v ss nc tck v ss tdi a a dq c v ss dq c v ss dq c dq c nc v ss v ss v ss v ss nc v ss a1 dq d dq d nc nc v ddq v ss tms 891011 a adv a adsc nc oe adsp a nc/576m v ss v ddq nc/1g dqp b v ddq v dd dq b dq b dq b nc dq b nc dq a dq a v dd v ddq v dd v ddq dq b v dd nc v dd dq a v dd v ddq dq a v ddq v dd v dd v ddq v dd v ddq dq a v ddq a a v ss a a a dq b dq b dq b zz dq a dq a dqp a dq a a v ddq a a0 a v ss a 234 567 1 a b c d e f g h j k l m n p r tdo nc/288m nc/144m nc nc dqp b nc dq b ace 1 nc ce 3 bw b bwe a ce 2 nc dq b dq b mode nc dq b dq b nc nc nc a a v ddq nc bw a clk gw v ss v ss v ss v ss v ddq v ss v dd v ss v ss v ss v ss v ss v ss v ss v ddq v ddq nc v ddq v ddq v ddq v ddq a a v dd v ss v dd v ss v ss v ddq v dd v ss v dd v ss v dd v ss v ss v ss v dd v dd v ss v dd v ss v ss nc tck a0 v ss tdi a a dq b v ss nc v ss dq b nc nc v ss v ss v ss v ss nc v ss a1 dq b nc nc nc v ddq v ss tms 891011 a adv a adsc a oe adsp a nc/576m v ss v ddq nc/1g dqp a v ddq v dd nc dq a dq a nc nc nc dq a nc v dd v ddq v dd v ddq dq a v dd nc v dd nc v dd v ddq dq a v ddq v dd v dd v ddq v dd v ddq nc v ddq a a v ss a a a dq a nc nc zz dq a nc nc dq a a v ddq a a [+] feedback [+] feedback
cy7c1481v33 cy7c1483v33 cy7c1487v33 document #: 38-05284 rev. *h page 6 of 30 pin configurations (continued) cy7c1487v33 (1m 72) a b c d e f g h j k l m n p r t u v w 123456789 11 10 dq g dq g dq g dq g dq g dq g dq g dq g dq c dq c dq c dq c nc dqp g dq h dq h dq h dq h dq d dq d dq d dq d dqp d dqp c dq c dq c dq c dq c nc dq h dq h dq h dq h dqp h dq d dq d dq d dq d dq b dq b dq b dq b dq b dq b dq b dq b dq f dq f dq f dq f nc dqp f dq a dq a dq a dq a dq e dq e dq e dq e dqp a dqp b dq f dq f dq f dq f nc dq a dq a dq a dq a dqp e dq e dq e dq e dq e aadsp adv a nc nc a aa a a aa aa a a1 a0 a aa aa a nc/144m nc/288m nc/576m gw nc nc bws b bws f bws e bws a bws c bws g bws d bws h tms tdi tdo tck nc nc mode nc v ss v ss nc clk nc v ss v dd v dd v dd v dd v dd v dd v dd v dd v dd v dd v dd v dd v dd v ss v ss v ss v ss v ss v ss v ss v ss nc/1g v dd nc oe ce 3 ce 1 ce 2 adsc bw v ss v ss v ss v ss v ss v ss v ss zz v ss v ss v ss v ss nc v ddq v ss v ss nc v ss v ss v ss v ss v ss v ss nc v ss v ddq v ddq v ddq v ddq v ddq nc v ddq v ddq v ddq v ddq nc v ddq v ddq v ddq v ddq nc v ddq v ddq v ddq v ddq v ddq v ddq v ddq v ddq v ddq v ddq 209-ball fbga (14 x 22 x 1.76 mm) pinout [+] feedback [+] feedback
cy7c1481v33 cy7c1483v33 cy7c1487v33 document #: 38-05284 rev. *h page 7 of 30 pin definitions pin name io description a 0 , a 1 , a input- synchronous address inputs used to select one of the address locations . sampled at the rising edge of the clk if adsp or adsc is active low, and ce 1 , ce 2 , and ce 3 are sampled active. a [1:0] feed the two-bit counter. bw a ,bw b ,bw c ,bw d , bw e ,bw f ,bw g ,bw h input- synchronous byte write select inputs, active low . qualified with bwe to conduct byte writes to the sram. sampled on the rising edge of clk. gw input- synchronous global write enable input, active low . when asserted low on the rising edge of clk, a global write is conducted (all by tes are written, regardless of the values on bw x and bwe ). clk input- clock clock input . captures all synchronous inputs to the device. also used to increment the burst counter when adv is asserted low during a burst operation. ce 1 input- synchronous chip enable 1 input, active low . sampled on the rising edge of clk. used in conjunction with ce 2 and ce 3 to select or desele ct the device. adsp is ignored if ce 1 is high. ce 1 is sampled only when a new external address is loaded. ce 2 input- synchronous chip enable 2 input, active high . sampled on the rising edge of clk. used in conjunction with ce 1 and ce 3 to select or deselect the device. ce 2 is sampled only when a new external address is loaded. ce 3 input- synchronous chip enable 3 input, active low . sampled on the rising edge of clk. used in conjunction with ce 1 and ce 2 to select or dese lect the device. ce 3 is sampled only when a new external address is loaded. oe input- asynchronous output enable, asynchronous input, active low . controls the direction of the io pins. when low, the io pins behave as outputs. when deasserted high, io pins are tri-stated, and act as input data pins. oe is masked during the first clock of a read cycle when emerging from a deselected state. adv input- synchronous advance input signal, sampled on the rising edge of clk . when asserted, it automatically increments the address in a burst cycle. adsp input- synchronous address strobe from processor, sampled on the rising edge of clk, active low . when asserted low, addresses presented to the device are captured in the address registers. a [1:0] are also loaded into the burst counter. when adsp and adsc are both asserted, only adsp is recognized. asdp is ignored when ce 1 is deasserted high adsc input- synchronous address strobe from controller, sampled on the rising edge of clk, active low . when asserted low, addresses presented to the device are captured in the address registers. a [1:0] are also loaded into the burst counter. when adsp and adsc are both asserted, only adsp is recognized . bwe input- synchronous byte write enable input, active low . sampled on the rising edge of clk. this signal must be asserted low to conduct a byte write. zz input- asynchronous zz ?sleep? input, active high . when asserted high, places the device in a non-time-critical ?sleep? condition with data integrity preserved. for normal operation, this pin must be low or left floating. zz pin has an internal pull down. dq s io- synchronous bidirectional data io lines . as inputs, they feed into an on-chip data register that is triggered by the rising edge of clk. as outputs, they deliver the data contained in the memory location specified by the addresses presented during the previous clock rise of the read cycle. the directio n of the pins is controlled by oe . when oe is asserted low, the pins behave as outputs. when high, dq s and dqp x are placed in a tri-state condition.the outputs are auto matically tri-stated during the data portion of a write sequence, during the first clo ck when emerging from a deselected state, and when the device is deselected, regardless of the state of oe . dqp x io- synchronous bidirectional data parity i/o lines. functionally, these signals are identical to dq s . during write sequences, dqp x is controlled by bw x correspondingly. mode input-static selects burst order . when tied to gnd, selects linear burst sequence. when tied to v dd or left floating, selects interleaved burst sequence. this is a strap pin and must remain static during device operation. mode pin has an internal pull up. [+] feedback [+] feedback
cy7c1481v33 cy7c1483v33 cy7c1487v33 document #: 38-05284 rev. *h page 8 of 30 functional overview all synchronous inputs pass through input registers controlled by the rising edge of the clock. maximum access delay from the clock rise (t cdv ) is 6.5 ns (133-mhz device). the cy7c1481v33/cy7c1483v33/cy7c1487v33 supports secondary cache in systems usin g either a li near or inter- leaved burst sequence. the interleaved burst order supports pentium and i486? processors. the linear burst sequence is suited for processors that use a linear burst sequence. the burst order is user selectable, and is determined by sampling the mode input. accesses can be initiated with either the processor address strobe (adsp ) or the controller address strobe (adsc ). address advancement through the burst sequence is controlled by the adv input. a two-bit on-chip wraparound burst counter captures the first address in a burst sequence and automatically increments the address for the rest of the burst access. byte write operations are qualif ied with the byte write enable (bwe ) and byte write select (bwx ) inputs. a global write enable (gw ) overrides all byte write inputs and writes data to all four bytes. all writes are simplified with on-chip synchronous self timed write circuitry. three synchronous chip selects (ce 1 , ce 2 , ce 3 ) and an asynchronous output enable (oe ) provide easy bank selection and output tri-state co ntrol. adsp is ignored if ce 1 is high. single read accesses a single read access is initiated when the following conditions are satisfied at clock rise: (1) ce 1 , ce 2 , and ce 3 are all asserted active, and (2) adsp or adsc is asserted low (if the access is initiated by adsc , the write inputs must be deasserted during this first cycle). the address presented to the address inputs is latched into the address register and the burst counter/control logic and presented to the memory core. if the oe input is asserted low, the requested data is available at the data outputs a maximum to t cdv after clock rise. adsp is ignored if ce 1 is high. single write accesses initiated by adsp this access is initiated when the following conditions are satisfied at clock rise: (1) ce 1 , ce 2 , ce 3 are all asserted active, and (2) adsp is asserted low. the addresses presented are loaded into t he address register and the burst inputs (gw , bwe , and bw x ) are ignored during this first clock cycle. if the write inputs are asserted active (see ?truth table for read/write? on page 11 for appropriate states that indicate a write) on the next clock rise, the appropriate data is latched and written into the device. byte writes are supported. all ios are tri-stated during a byte write. because this is a common io device, the asynchronous oe input signal must be deasserted and the i/os must be tri-stated before the presentation of data to dq s . as a safety precaution, the data lines are tri-stated after a write cycle is detected, regardless of the state of oe . single write accesses initiated by adsc this write access is initiated when the following conditions are satisfied at cl ock rise: (1) ce 1 , ce 2 , and ce 3 are all asserted active, (2) adsc is asserted low, (3) adsp is deasserted high, and (4) the write input signals (gw , bwe , and bwx ) indicate a write access. adsc is ignored if adsp is active low. the addresses presented are loaded into the address register and the burst counter/control logic and delivered to the memory core. the information presented to dq s will be written into the specified address location. byte writes are supported. v dd power supply power supply inputs to the core of the device . v ddq io power supply power supply for the io circuitry . v ss ground ground for the core of the device . v ssq [2} i/o ground ground for the io circuitry . tdo jtag serial output synchronous serial data-out to the jtag circuit . delivers data on the negative edge of tck. if the jtag feature is not used, this pin s hould be left unconnected. this pin is not available on tqfp packages. tdi jtag serial input synchronous serial data-in to the jtag circuit . sampled on the rising edge of tck. if the jtag feature is not used, this pin can be left floating or connected to v dd through a pull up resistor. this pin is not available on tqfp packages. tms jtag serial input synchronous serial data-in to the jtag circuit . sampled on the rising edge of tck. if the jtag feature is not used, this pin c an be disconnected or connected to v dd . this pin is not available on tqfp packages. tck jtag clock clock input to the jtag circuit . if the jtag feature is no t used, this pin must be connected to v ss . this pin is not available on tqfp packages. nc - no connects . not internally connected to the die. 144m, 288m, 576m, and 1g are address expansion pins and are not internally connected to the die. pin definitions (continued) pin name io description note 2. applicable for tqfp package. for bga package v ss serves as ground for the core and the io circuitry. [+] feedback [+] feedback
cy7c1481v33 cy7c1483v33 cy7c1487v33 document #: 38-05284 rev. *h page 9 of 30 all ios are tri-stated when a write is detected, even a byte write. because this is a common io device, the asynchronous oe input signal must be deasserted and the ios must be tri-stated before the presentation of data to dq s . as a safety precaution, the data lines are tri-stated once a write cycle is detected, regardless of the state of oe . burst sequences the cy7c1481v33/cy7c1483v33/cy7c1487v33 provides an on-chip two-bit wraparound burst counter inside the sram. the burst counter is fed by a[1: 0], and can follow either a linear or interleaved burst order. the burst order is determined by the state of the mode input. a low on mode selects a linear burst sequence. a high on mode selects an interleaved burst order. leaving mode unc onnected causes the device to default to a interleaved burst sequence. sleep mode the zz input pin is asynchronous. asserting zz places the sram in a power conservation ?sleep? mode. two clock cycles are required to enter into or exit from this ?sleep? mode. while in this mode, data integrity is guaranteed. accesses pending when entering the ?sleep? mode are not considered valid nor is the completion of the operation guaranteed. the device must be deselected before entering the ?sleep? mode. ce 1 , ce 2 , ce 3 , adsp , and adsc must remain inactive for the duration of t zzrec after the zz input returns low. interleaved burst address table (mode = floating or v dd ) first address a1: a0 second address a1: a0 third address a1: a0 fourth address a1: a0 00 01 10 11 01 00 11 10 10 11 00 01 11 10 01 00 linear burst address table (mode = gnd) first address a1: a0 second address a1: a0 third address a1: a0 fourth address a1: a0 00 01 10 11 01 10 11 00 10 11 00 01 11 00 01 10 zz mode electrical characteristics parameter description test conditions min max unit i ddzz sleep mode standby current zz > v dd ? 0.2v 150 ma t zzs device operation to zz zz > v dd ? 0.2v 2t cyc ns t zzrec zz recovery time zz < 0.2v 2t cyc ns t zzi zz active to sleep current t his parameter is sampled 2t cyc ns t rzzi zz inactive to exit sleep current this parameter is sampled 0 ns [+] feedback [+] feedback
cy7c1481v33 cy7c1483v33 cy7c1487v33 document #: 38-05284 rev. *h page 10 of 30 truth table the truth table for cy7c1481v33, cy7c1483v33, and cy7c1487v33 follows. [3, 4, 5, 6, 7] cycle description address used ce 1 ce 2 ce 3 zz adsp adsc adv write oe clk dq deselected cycle, power down none h x x l x l x x x l-h tri-state deselected cycle, power down none l l x l l x x x x l-h tri-state deselected cycle, power down none l x h l l x x x x l-h tri-state deselected cycle, power down none l l x l h l x x x l-h tri-state deselected cycle, power down none x x x l h l x x x l-h tri-state sleep mode, power down none x x x h x x x x x x tri-state read cycle, begin burst external l h l l l x x x l l-h q read cycle, begin burst external l h l l l x x x h l-h tri-state write cycle, begin burst external l h l l h l x l x l-h d read cycle, begin burst external l h l l h l x h l l-h q read cycle, begin burst external l h l l h l x h h l-h tri-state read cycle, continue burst next x x x l h h l h l l-h q read cycle, continue burst next x x x l h h l h h l-h tri-state read cycle, continue burst next h x x l x h l h l l-h q read cycle, continue burst next h x x l x h l h h l-h tri-state write cycle, continue burst next x x x l h h l l x l-h d write cycle, continue burst next h x x l x h l l x l-h d read cycle, suspend burst current x x x l h h h h l l-h q read cycle, suspend burst current x x x l h h h h h l-h tri-state read cycle, suspend burst current h x x l x h h h l l-h q read cycle, suspend burst current h x x l x h h h h l-h tri-state write cycle, suspend burst current x x x l h h h l x l-h d write cycle, suspend burst current h x x l x h h l x l-h d notes 3. x = do not care, h = logic high, l = logic low. 4. write = l when any one or more byte write enable signals and bwe = l or gw = l. write = h when all byte write enable signals, bwe , gw = h. 5. the dq pins are controlled by the current cycle and the oe signal. oe is asynchronous and is not sampled with the clock. 6. the sram always initiates a read cycle when adsp is asserted, regardless of the state of gw , bwe , or bw x . writes may occur only on subsequent clocks after the adsp or with the assertion of adsc . as a result, oe must be driven high prior to the start of the write cycle to enable the outputs to tri-state. oe is a do not care for the remainder of the write cycle. 7. oe is asynchronous and is not sampled with the clock rise. it is masked internally during writ e cycles. during a read cycle all d ata bits are tri-state when oe is inactive or when the device is deselected, and all data bits behave as outputs when oe is active (low). [+] feedback [+] feedback
cy7c1481v33 cy7c1483v33 cy7c1487v33 document #: 38-05284 rev. *h page 11 of 30 truth table for read/write the read-write truth table for cy7c1481v33 follows. [3, 8] function gw bwe bw d bw c bw b bw a read h h x x x x read hlhhhh write byte a (dq a , dqp a ) hlhhhl write byte b(dq b , dqp b )hlhhlh write bytes a, b (dq a , dq b , dqp a , dqp b )hlhhll write byte c (dq c , dqp c ) hlhlhh write bytes c, a (dq c , dq a, dqp c , dqp a ) hlhlhl write bytes c, b (dq c , dq b, dqp c , dqp b )hlhllh write bytes c, b, a (dq c , dq b , dq a, dqp c , dqp b , dqp a )h l h l l l write byte d (dq d , dqp d ) hl lhhh write bytes d, a (dq d , dq a, dqp d , dqp a )hllhhl write bytes d, b (dq d , dq a, dqp d , dqp a )hllhlh write bytes d, b, a (dq d , dq b , dq a, dqp d , dqp b , dqp a )h l l h l l write bytes d, b (dq d , dq b, dqp d , dqp b )hlllhh write bytes d, b, a (dq d , dq c , dq a, dqp d , dqp c , dqp a )h l l l h l write bytes d, c, a (dq d , dq b , dq a, dqp d , dqp b , dqp a )h l l l l h write all bytes h l l l l l write all bytes l x x x x x truth table for read/write the read-write truth table for cy7c1483v33 follows. [3, 8] function gw bwe bw b bw a read h h x x read h l h h write byte a - (dq a and dqp a )hlhl write byte b - (dq b and dqp b )hllh write all bytes h l l l write all bytes l x x x truth table for read/write the read-write truth table for cy7c1487v33 follows. [3, 8] function gw bwe bw x [9] read h h x read h l all bw = h write byte x ? (dq x and dqp x )hll write all bytes h l all bw = l write all bytes l x x notes 8. table only lists a partial listing of the byte write combinations. any combination of bw x is valid. an appropriate write is performed based on which byte write is active. 9. bw x represents any byte write signal bw x .to enable any byte write bw x , a logic low signal must be applied at clock rise. any number of byte writes can be enabled at the same time for any given write. [+] feedback [+] feedback
cy7c1481v33 cy7c1483v33 cy7c1487v33 document #: 38-05284 rev. *h page 12 of 30 ieee 1149.1 serial boundary scan (jtag) the cy7c1481v33/cy7c1483v33/cy7c1487v33 incorpo- rates a serial boundary scan test access port (tap). this port operates in accordance with ieee standard 1149.1-1990 but does not have the set of functions required for full 1149.1 compliance. these functions fr om the ieee specification are excluded because their inclusion places an added delay in the critical speed path of the sram . note that the tap controller functions in a manner that does not conflict with the operation of other devices using 1149.1 fully compliant taps. the tap operates using jedec standard 3.3v or 2.5v io logic levels. the cy7c1481v33/cy7c1483v 33/cy7c1487v33 contains a tap controller, instruction register, boundary scan register, bypass register, and id register. disabling the jtag feature it is possible to operate the sram without using the jtag feature. to disable the tap controller, tie tck low (v ss ) to prevent device clocking. tdi and tms are internally pulled up and may be unconnected. they may alternatively be connected to v dd through a pull up resistor. tdo must be left unconnected. at power up, the device comes up in a reset state, which does not interfere with the operation of the device. the 0/1 next to each state repr esents the value of tms at the rising edge of tck. test access port (tap) test clock (tck) the test clock is used only with the tap controller. all inputs are captured on the rising edge of tck. all outputs are driven from the falling edge of tck. test mode select (tms) the tms input is used to give commands to the tap controller and is sampled on the rising edge of tck. you can leave this ball unconnected if the tap is not used. the ball is pulled up internally, resulting in a logic high level. test data-in (tdi) the tdi ball is used to serially input information into the registers and can be connected to the input of any of the registers. the register between tdi and tdo is chosen by the instruction that is loaded into the tap instruction register. for information about loading the instruction register, see the tap controller state diagram . tdi is internally pulled up and can be unconnected if the tap is unused in an application. tdi is connected to the most significant bit (msb) of any register. (see tap controller block diagram .) test data-out (tdo) the tdo output ball serially clo cks data-out from the registers. whether the output is active depends on the current state of the tap state machine. the output changes on the falling edge of tck. tdo is connected to th e least significant bit (lsb) of any register. (see tap controller state diagram .) performing a tap reset to perform a reset, force tms high (v dd ) for five rising edges of tck. this reset doe s not affect the operation of the sram and may be performed while the sram is operating. at power up, the tap is reset internally to ensure that tdo comes up in a high-z state. tap registers registers are connected between the tdi and tdo balls and allow data to be scanned into and out of the sram test circuitry. only one register can be selected at a time through the instruction register. data is serially loaded into the tdi ball on the rising edge of tck. data is output on the tdo ball on the falling edge of tck. instruction register three-bit instructions can be seri ally loaded into the instruction register. this register is loaded when it is placed between the tdi and tdo balls, as shown in the ?tap controller block diagram? on page 12 . at power up, the instruction register is loaded with the idcode instruction. it is also loaded with the tap controller state diagram test-logic reset run-test/ idle select dr-scan select ir-scan capture-dr shift-dr capture-ir shift-ir exit1-dr pause-dr exit1-ir pause-ir exit2-dr update-dr exit2-ir update-ir 1 1 1 0 1 1 0 0 1 1 1 0 0 0 0 0 0 0 0 0 1 0 1 1 0 1 0 1 1 1 1 0 tap controller block diagram bypass register 0 instruction register 0 1 2 identication register 0 1 2 29 30 31 . . . boundary scan register 0 1 2 . . x . . . selection circuitry tck tms tap controller tdi tdo selection circuitry [+] feedback [+] feedback
cy7c1481v33 cy7c1483v33 cy7c1487v33 document #: 38-05284 rev. *h page 13 of 30 idcode instruction if the contro ller is placed in a reset state, as described in the previous section. when the tap controller is in the capture-ir state, the two least significant bits are loaded with a binary ?01? pattern to enable fault isolation of the board level serial test data path. bypass register to save time when serially shifting data through registers, it is sometimes advantageous to skip certain chips. the bypass register is a single-bit register that can be placed between the tdi and tdo balls. this allows data to be shifted through the sram with minimal delay. the bypass register is set low (v ss ) when the bypass instruction is executed. boundary scan register the boundary scan register is connected to all the input and bidirectional balls on the sram. the x36 configuration has a 73-bit-long register, and t he x18 configuration has a 54-bit-long register. the boundary scan register is lo aded with the contents of the ram i/ ring when the tap controll er is in the capture-dr state and is then placed between the tdi and tdo balls when the controller is moved to the shift-dr state. the extest, sample/preload and sample z instructions can be used to capture the contents of the io ring. the boundary scan order tables show the order in which the bits are connected. each bit corresponds to one of the bumps on the sram package. the msb of the register is connected to tdi and the lsb is connected to tdo. identification (id) register the id register is loaded with a vendor-specific, 32-bit code during the capture-dr state when the idcode command is loaded in the instruction regi ster. the idcode is hardwired into the sram and can be shifted out when the tap controller is in the shift-dr state. the id register has a vendor code and other information described in ?identification register defini- tions? on page 15 . tap instruction set overview eight different instructions are possible with the three-bit instruction register. all combinations are listed in ?identification codes? on page 16 . three of these instructions are listed as reserved and must not be used. the other five instructions are described in detail below. the tap controller used in this sram is not fully compliant to the 1149.1 convention because some of the mandatory 1149.1 instructions are not fully implemented. the tap controller cannot be used to load address data or control signals into the sram and cannot preload the io buffers. the sram does not implement the 1149.1 commands extest or intest or the preload portion of sample/preload; rather, it performs a capture of the io ring when these instructions are executed. instructions are loaded into the tap controller during the shift-ir state, when the instruct ion register is placed between tdi and tdo. during this state, instructions are shifted through the instruction register through the tdi and tdo balls. to execute the instruction once it is shifted in, the tap controller must be moved into the update-ir state. extest extest is a mandatory 1149.1 instruction, which is to be executed whenever the instructi on register is loaded with all zeros. extest is not implemented in this sram tap controller, and therefore this device is not compliant to 1149.1. the tap controller does recognize an all-zero instruction. when an extest instruction is loaded into the instruction register, the sram responds as if a sample/preload instruction is loaded. there is one difference between the two instructions. unlike the sample/preload instruction, extest places the sram outputs in a high-z state. idcode the idcode instruction causes a vendor-specific, 32-bit code to be loaded into the instruction register. it also places the instruction register between the tdi and tdo balls and enables the idcode to be shifted out of the device when the tap controller enters the shift-dr state. the idcode instruction is loaded into the instruction register at power up or whenever the tap controller is in a test logic reset state. sample z the sample z instruction causes the boundary scan register to be connected between the tdi and tdo balls when the tap controller is in a shift-dr state. it also places all sram outputs into a high-z state. sample/preload sample/preload is a 1149.1 m andatory instruction. the preload portion of this instru ction is not implemented, so the device tap controller is not fully 1149.1 compliant. when the sample/preload instruction is loaded into the instruction register and the tap controller is in the capture-dr state, a snapshot of data on the inputs and bidirectional balls is captured in the boundary scan register. be aware that the tap controller clock can only operate at a frequency up to 10 mhz, while the sram clock operates more than an order of magnitude faster. because there is a large difference in the clock frequencies, it is possible that during the capture-dr state, an input or output may undergo a transition. the tap may then try to capture a signal while in transition (metastable state). this does not harm the device, but there is no guarantee as to the value that may be captured. repeatable results may not be possible. to guarantee that the boundary scan register captures the correct value of a signal, the sram signal must be stabilized long enough to meet the tap controller?s capture setup plus hold time (t cs plus t ch ). the sram clock input might not be captured correctly if there is no way in a design to stop (or slow) the clock during a sample/preload instruction. if th is is an issue, it is still possible to capture all other signals and simply ignore the value of the clk captured in the boundary scan register. [+] feedback [+] feedback
cy7c1481v33 cy7c1483v33 cy7c1487v33 document #: 38-05284 rev. *h page 14 of 30 after the data is captured, it is possible to shift out the data by putting the tap into the shift-dr state. this places the boundary scan register between the tdi and tdo balls. note that because the preload part of the command is not implemented, putting the tap to the update-dr state while performing a sample/preload instruction has the same effect as the pause-dr command. bypass when the bypass instruction is loaded in the instruction register and the tap is placed in a shift-dr state, the bypass register is placed between the tdi and tdo balls. the advantage of the bypass instructio n is that it shortens the boundary scan path when multiple devices are connected together on a board. reserved these instructions are not im plemented but are reserved for future use. do not use these instructions. tap timing t tl test clock (tck) 123456 test mode select (tms) t th test data-out (tdo) t cyc test data-in (tdi) t tmsh t tmss t tdih t tdis t tdox t tdov dont care undefined tap ac switching characteristics over the operating range [10,11] parameter description min max unit clock t tcyc tck clock cycle time 50 ns t tf tck clock frequency 20 mhz t th tck clock high time 20 ns t tl tck clock low time 20 ns output times t tdov tck clock low to tdo valid 10 ns t tdox tck clock low to tdo invalid 0 ns set-up times t tmss tms set-up to tck clock rise 5 ns t tdis tdi set-up to tck clock rise 5 ns t cs capture set-up to tck rise 5 hold times t tmsh tms hold after tck clock rise 5 ns t tdih tdi hold after clock rise 5 ns t ch capture hold after clock rise 5 ns notes 10. t cs and t ch refer to the setup and hold time requirements of latching data from the boundary scan register. 11. test conditions are specified using the load in tap ac test conditions. t r /t f = 1 n.s. [+] feedback [+] feedback
cy7c1481v33 cy7c1483v33 cy7c1487v33 document #: 38-05284 rev. *h page 15 of 30 3.3v tap ac test conditions input pulse levels ................................................ v ss to 3.3v input rise and fall times ......... .......................................... 1 ns input timing referenc e levels ...........................................1.5v output reference levels...................................................1.5v test load termination supply vo ltage...............................1.5v 2.5v tap ac test conditions input pulse levels................................................. v ss to 2.5v input rise and fall time .....................................................1 ns input timing reference levels... ...................................... 1.25v output reference levels .......... ...................................... 1.25v test load termination supply voltage ............................ 1.25v 3.3v tap ac output load equivalent tdo 1.5v 20pf z = 50 ? o 50 ? 2.5v tap ac output load equivalent tdo 1.25v 20pf z = 50 ? o 50 ? (0c < t a < +70c; v dd = 3.135v to 3.6v unless otherwise noted) [12] parameter description conditions min max unit v oh1 output high voltage i oh = ?4.0 ma v ddq = 3.3v 2.4 v i oh = ?1.0 ma v ddq = 2.5v 2.0 v v oh2 output high voltage i oh = ?100 a v ddq = 3.3v 2.9 v v ddq = 2.5v 2.1 v v ol1 output low voltage i ol = 8.0 ma v ddq = 3.3v 0.4 v i ol = 1.0 ma v ddq = 2.5v 0.4 v v ol2 output low voltage i ol = 100 a v ddq = 3.3v 0.2 v v ddq = 2.5v 0.2 v v ih input high voltage v ddq = 3.3v 2.0 v dd + 0.3 v v ddq = 2.5v 1.7 v dd + 0.3 v v il input low voltage v ddq = 3.3v ?0.3 0.8 v v ddq = 2.5v ?0.3 0.7 v i x input load current gnd < v in < v ddq ?5 5 a identification register definitions bit# 24 is ?1? in the id register definitions for both 2.5v and 3.3v versions of the device. instruction field cy7c1481v33 (2m x 36) cy7c1483v33 (4m x18) cy7c1487v33 (1m x72) description revision number (31:29) 000 000 000 describes the version number device depth (28:24) 01011 01011 01011 reserved for internal use architecture/memory type(23:18) 000001 000001 0 00001 defines memory type and architecture bus width/density (17:12) 100100 010100 110100 defines width and density cypress jedec id code (11:1) 00000110100 00000110100 00000110100 enables unique identification of sram vendor id register presence indicator (0) 1 1 1 in dicates the presence of an id register note 12. all voltages refer to v ss (gnd). [+] feedback [+] feedback
cy7c1481v33 cy7c1483v33 cy7c1487v33 document #: 38-05284 rev. *h page 16 of 30 scan register sizes register name bit size (x36) bi t size (x18) bit size (x72) instruction 3 3 3 bypass 1 1 1 id 32 32 32 boundary scan order -165fbga 73 54 - boundary scan order -209 bga - - 112 identification codes instruction code description extest 000 captures io ring contents. idcode 001 loads the id register with the vendor id code and places the register between tdi and tdo. this operation does not affect sram operations. sample z 010 captures io ring contents. places the boundary scan register between tdi and tdo. forces all sram output drivers to a high-z state. reserved 011 do not use: this instruct ion is reserved for future use. sample/preload 100 captures io ring contents. plac es the boundary scan register between tdi and tdo. does not affect sram operation. reserved 101 do not use: this instruct ion is reserved for future use. reserved 110 do not use: this instruct ion is reserved for future use. bypass 111 places the bypass register between tdi and tdo. this operation does not affect sram operations. boundary scan exit order (2m x 36) bit # 165-ball id bit # 165-ball id bit # 165-ball id bit # 165-ball id 1 c1 21 r3 41 l10 61 b8 2d1 22 p2 42k11 62 a7 3e1 23 r4 43j11 63 b7 4d2 24 p6 44k10 64 b6 5 e2 25 r6 45 j10 65 a6 6f1 26 n6 46h11 66 b5 7g1 27p11 47g11 67 a5 8f2 28 r8 48f11 68 a4 9g2 29 p3 49e11 69 b4 10 j1 30 p4 50 d10 70 b3 11 k1 31 p8 51 d11 71 a3 12 l1 32 p9 52 c11 72 a2 13 j2 33 p10 53 g10 73 b2 14 m1 34 r9 54 f10 15 n1 35 r10 55 e10 16 k2 36 r11 56 a10 17 l2 37 n11 57 b10 18 m2 38 m11 58 a9 19 r1 39 l11 59 b9 20 r2 40 m10 60 a8 [+] feedback [+] feedback
cy7c1481v33 cy7c1483v33 cy7c1487v33 document #: 38-05284 rev. *h page 17 of 30 boundary scan exit order (4m x 18) bit # 165-ball id bit # 165-ball id bit # 165-ball id 1d2 19r8 37 c11 2e2 20p3 38 a11 3f2 21p4 39 a10 4g2 22p8 40 b10 5j1 23p9 41 a9 6 k1 24 p10 42 b9 7l1 25r9 43 a8 8m1 26r10 44 b8 9n1 27r11 45 a7 10 r1 28 m10 46 b7 11 r2 29 l10 47 b6 12 r3 30 k10 48 a6 13 p2 31 j10 49 b5 14 r4 32 h11 50 a4 15 p6 33 g11 51 b3 16 r6 34 f11 52 a3 17 n6 35 e11 53 a2 18 p11 36 d11 54 b2 [+] feedback [+] feedback
cy7c1481v33 cy7c1483v33 cy7c1487v33 document #: 38-05284 rev. *h page 18 of 30 boundary scan exit order (1m x 72) bit # 209-ball id bit # 209-ball id bit # 209-ball id bit # 209-ball id 1 a1 29 t1 57 v10 85 c11 2a2 30t2 58u11 86c10 3 b1 31 u1 59 u10 87 b11 4b2 32u2 60t11 88b10 5 c1 33 v1 61 t10 89 a11 6c2 34v2 62r11 90a10 7 d1 35 w1 63 r10 91 a9 8d2 36w2 64p11 92u8 9 e1 37 t6 65 p10 93 a7 10 e2 38 v3 66 n11 94 a5 11 f1 39 v4 67 n10 95 a6 12 f2 40 u4 68 m11 96 d6 13 g1 41 w5 69 m10 97 b6 14 g2 42 v6 70 l11 98 d7 15 h1 43 w6 71 l10 99 k3 16 h2 44 u3 72 p6 100 a8 17 j1 45 u9 73 j11 101 b4 18 j2 46 v5 74 j10 102 b3 19 l1 47 u5 75 h11 103 c3 20 l2 48 u6 76 h10 104 c4 21 m1 49 w7 77 g11 105 c8 22 m2 50 v7 78 g10 106 c9 23 n1 51 u7 79 f11 107 b9 24 n2 52 v8 80 f10 108 b8 25 p1 53 v9 81 e10 109 a4 26 p2 54 w11 82 e11 110 c6 27 r2 55 w10 83 d11 111 b7 28 r1 56 v11 84 d10 112 a3 [+] feedback [+] feedback
cy7c1481v33 cy7c1483v33 cy7c1487v33 document #: 38-05284 rev. *h page 19 of 30 maximum ratings exceeding maximum ratings may impair the useful life of the device. these user guidelines are not tested. storage temperature ................................. ?65 c to +150 c ambient temperature with power applied............................................. ?55 c to +125 c supply voltage on v dd relative to gnd........ ?0.3v to +4.6v supply voltage on v ddq relative to gnd ...... ?0.3v to +v dd dc voltage applied to outputs in tri-state........................................... ?0.5v to v ddq + 0.5v dc input voltage ................................... ?0.5v to v dd + 0.5v current into outputs (low).... ..................................... 20 ma static discharge voltage......... ........... ............ ........... >2001v (mil-std-883, method 3015) latch up current .................................................... >200 ma operating range range ambient temperature v dd v ddq commercial 0c to +70c 3.3v ?5%/+10% 2.5v ? 5% to v dd industrial ?40c to +85c electrical characteristics over the operating range [13, 14] parameter description test conditions min max unit v dd power supply voltage 3.135 3.6 v v ddq io supply voltage for 3.3v i/o 3.135 v dd v for 2.5v i/o 2.375 2.625 v v oh output high voltage for 3.3v i/o, i oh = ?4.0 ma 2.4 v for 2.5v i/o, i oh = ?1.0 ma 2.0 v v ol output low voltage for 3.3v i/o, i ol = 8.0 ma 0.4 v for 2.5v i/o, i ol = 1.0 ma 0.4 v v ih input high voltage [13] for 3.3v i/o 2.0 v dd + 0.3v v for 2.5v i/o 1.7 v dd + 0.3v v v il input low voltage [13] for 3.3v i/o ?0.3 0.8 v for 2.5v i/o ?0.3 0.7 v i x input leakage current except zz and mode gnd v i v ddq ?5 5 a input current of mode input = v ss ?30 a input = v dd 5 a input current of zz input = v ss ?5 a input = v dd 30 a i oz output leakage current gnd v i v dd, output disabled ?5 5 a i dd v dd operating supply current v dd = max, i out = 0 ma, f = f max = 1/t cyc 7.5-ns cycle, 133 mhz 335 ma 10-ns cycle, 100 mhz 305 ma i sb1 automatic ce power down current?ttl inputs max v dd , device deselected, v in v ih or v in v il , f = f max, inputs switching 7.5-ns cycle, 133 mhz 200 ma 10-ns cycle, 100 mhz 200 ma i sb2 automatic ce power down current?cmos inputs max v dd , device deselected, v in v dd ? 0.3v or v in 0.3v, f = 0, inputs static all speeds 150 ma i sb3 automatic ce power down current?cmos inputs max v dd , device deselected, v in v ddq ? 0.3v or v in 0.3v, f = f max , inputs switching 7.5-ns cycle, 133 mhz 200 ma 10-ns cycle, 100 mhz 200 ma i sb4 automatic ce power down current?ttl inputs max v dd , device deselected, v in v dd ? 0.3v or v in 0.3v, f = 0, inputs static all speeds 165 ma notes 13. overshoot: v ih (ac) < v dd +1.5v (pulse width less than t cyc /2). undershoot: v il (ac) > ?2v (pulse width less than t cyc /2). 14. t power-up : assumes a linear ramp from 0v to v dd (min) within 200 ms. during this time v ih < v dd and v ddq < v dd . [+] feedback [+] feedback
cy7c1481v33 cy7c1483v33 cy7c1487v33 document #: 38-05284 rev. *h page 20 of 30 capacitance tested initially and after any design or proc ess change that may affect these parameters. parameter description test conditions 100 tqfp max 165 fbga max 209 fbga max unit c address address input capacitance t a = 25 c, f = 1 mhz, v dd = 3.3v v ddq = 2.5v 666pf c data data input capacitance 5 5 5 pf c ctrl control input capacitance 8 8 8 pf c clk clock input capacitance 6 6 6 pf c i/o input/output capacitance 5 5 5 pf thermal resistance tested initially and after any design or proc ess change that may affect these parameters. parameter description test conditions 100 tqfp package 165 fbga package 209 fbga package unit ja thermal resistance (junction to ambient) test conditions follow standard test methods and procedures for measuring thermal impedance, per eia/jesd51. 24.63 16.3 15.2 c/w jc thermal resistance (junction to case) 2.28 2.1 1.7 c/w ac test loads and waveforms output r = 317 ? r = 351 ? 5pf including jig and scope (a) (b) output r l = 50 ? z 0 = 50 ? v l = 1.5v 3.3v all input pulses v ddq gnd 90% 10% 90% 10% 1 ns 1 ns (c) output r = 1667 ? r = 1538 ? 5pf including jig and scope (a) (b) output r l = 50 ? z 0 = 50 ? v l = 1.25v 2.5v all input pulses v ddq gnd 90% 10% 90% 10% 1 ns 1 ns (c) 3.3v io test load 2.5v io test load [+] feedback [+] feedback
cy7c1481v33 cy7c1483v33 cy7c1487v33 document #: 38-05284 rev. *h page 21 of 30 switching characteristics over the operating range. [15, 16] parameter description 133 mhz 100 mhz unit min max min max t power v dd (typical) to the first access [17] 11ms clock t cyc clock cycle time 7.5 10 ns t ch clock high 2.5 3.0 ns t cl clock low 2.5 3.0 ns output times t cdv data output valid after clk rise 6.5 8.5 ns t doh data output hold after clk rise 2.5 2.5 ns t clz clock to low-z [18, 19, 20] 3.0 3.0 ns t chz clock to high-z [18, 19, 20] 3.8 4.5 ns t oev oe low to output valid 3.0 3.8 ns t oelz oe low to output low-z [18, 19, 20] 00ns t oehz oe high to output high-z [18, 19, 20] 3.0 4.0 ns setup times t as address setup before clk rise 1.5 1.5 ns t ads adsp , adsc setup before clk rise 1.5 1.5 ns t advs adv setup before clk rise 1.5 1.5 ns t wes gw , bwe , bw x setup before clk rise 1.5 1.5 ns t ds data input setup before clk rise 1.5 1.5 ns t ces chip enable setup 1.5 1.5 ns hold times t ah address hold after clk rise 0.5 0.5 ns t adh adsp , adsc hold after clk rise 0.5 0.5 ns t weh gw , bwe , bw x hold after clk rise 0.5 0.5 ns t advh adv hold after clk rise 0.5 0.5 ns t dh data input hold after clk rise 0.5 0.5 ns t ceh chip enable hold after clk rise 0.5 0.5 ns notes 15. timing reference level is 1.5v when v ddq = 3.3v and is 1.25v when v ddq = 2.5v. 16. test conditions shown in (a) of ?ac test loads and waveforms? on page 20 unless otherwise noted. 17. this part has an internal voltage regulator; t power is the time that the power must be supplied above v dd (minimum) initially, before a read or write operation can be initiated. 18. t chz , t clz , t oelz , and t oehz are specified with ac test conditions shown in part (b) of ?ac test loads and waveforms? on page 20 . transition is measured 200 mv from steady-state voltage. 19. at any supplied voltage and temperature, t oehz is less than t oelz and t chz is less than t clz to eliminate bus contention between srams when sharing the same data bus. these specifications do not impl y a bus contention condition, bu t reflect parameters guaranteed over worst case user conditions. device is designed to achieve high-z before low-z under the same system conditions. 20. this parameter is sampled and not 100% tested. [+] feedback [+] feedback
cy7c1481v33 cy7c1483v33 cy7c1487v33 document #: 38-05284 rev. *h page 22 of 30 timing diagrams figure 1. read cycle timing [21] t cyc t cl clk t adh t ads address t ch t ah t as a1 t ceh t ces data out (q) high-z t clz t doh t cdv t oehz t cdv single read burst read t oev t oelz t chz burst wraps around to its initial state t advh t advs t weh t wes t adh t ads q(a2) q(a2 + 1) q(a2 + 2) q(a1) q(a2) q(a2 + 1) q(a2 + 2) q(a2 + 3) a2 adv suspends burst deselect cycle dont care undefined adsp adsc gw, bwe, bw x ce adv oe note 21. on this diagram, when ce is low: ce 1 is low, ce 2 is high, and ce 3 is low. when ce is high: ce 1 is high, ce 2 is low, or ce 3 is high. [+] feedback [+] feedback
cy7c1481v33 cy7c1483v33 cy7c1487v33 document #: 38-05284 rev. *h page 23 of 30 figure 2. write cycle timing [21, 22] timing diagrams (continued) t cyc t cl clk t adh t ads address t ch t ah t as a1 t ceh t ces high-z burst read burst write d(a2) d(a2 + 1) d(a2 + 1) d(a1) d(a3) d(a3 + 1) d(a3 + 2) d(a2 + 3) a2 a3 extended burst write d(a2 + 2) single write t adh t ads t adh t ads t oehz t advh t advs t weh t wes t dh t ds t weh t wes byte write signals are ignored for rst cycle when adsp initiates burst adsc extends burst adv suspends burst dont care undefined adsp adsc bwe, bw x gw ce adv oe data in (d) d ata out (q) note 22. full width write can be initiated by either gw low; or by gw high, bwe low, and bw x low. [+] feedback [+] feedback
cy7c1481v33 cy7c1483v33 cy7c1487v33 document #: 38-05284 rev. *h page 24 of 30 figure 3. read/write cycle timing [21, 23, 24] timing diagrams (continued) t cyc t cl clk t adh t ads address t ch t ah t as a2 t ceh t ces single write d(a3) a3 a4 burst read back-to-back reads high-z q(a2) q(a4) q(a4+1) q(a4+2) q(a4+3) t weh t wes t oehz t dh t ds t cdv t oelz a1 a5 a6 d(a5) d(a6) q(a1) back-to-back writes dont care undefined adsp adsc bwe, bw x ce adv oe data in (d) data out (q) notes 23. the data bus (q) remains in high-z following a write cycle, unless a new read access is initiated by adsp or adsc . 24. gw is high. [+] feedback [+] feedback
cy7c1481v33 cy7c1483v33 cy7c1487v33 document #: 38-05284 rev. *h page 25 of 30 figure 4. zz mode timing [25, 26] timing diagrams (continued) t zz i supply clk zz t zzrec a ll inputs (except zz) dont care i ddzz t zzi t rzzi outputs (q) high-z deselect or read only notes 25. device must be deselected when entering zz mode. see ?truth table? on page 10 for all possible signal conditions to deselect the device. 26. dqs are in high-z when exiting zz sleep mode. [+] feedback [+] feedback
cy7c1481v33 cy7c1483v33 cy7c1487v33 document #: 38-05284 rev. *h page 26 of 30 ordering information not all of the speed, package, and temperature ranges are a vailable. please contact your local sales representative or visit www.cypress.com for actual prod ucts offered. speed (mhz) ordering code package diagram part and package type operating range 133 cy7c1481v33-133axc 51-85050 100-pin thin quad flat pack (14 x 20 x 1.4 mm) pb-free commercial cy7c1483v33-133axc cy7c1481v33-133bzc 51-85165 165-ball fine-pitch ball grid array (15 x 17 x 1.4 mm) cy7c1483v33-133bzc cy7c1481v33-133bzxc 51-85165 165-ball fine-pitch ball grid array (15 x 17 x 1.4 mm) pb-free cy7c1483v33-133bzxc cy7c1487v33-133bgc 51-85167 209-ball fine-pit ch ball grid array (14 22 1.76 mm) cy7c1487v33-133bgxc 209-ball fine-pitch ball grid array (14 22 1.76 mm) pb-free cy7c1481v33-133axi 51-85050 100-pin thin quad flat pack (14 x 20 x 1.4 mm) pb-free lndustrial cy7c1483v33-133axi cy7c1481v33-133bzi 51-85165 165-ball fine-pitch ball grid array (15 x 17 x 1.4 mm) cy7c1483v33-133bzi CY7C1481V33-133BZXI 51-85165 165-ball fine-pitch ball grid array (15 x 17 x 1.4 mm) pb-free cy7c1483v33-133bzxi cy7c1487v33-133bgi 51-85167 209-ball fine-pit ch ball grid array (14 22 1.76 mm) cy7c1487v33-133bgxi 209-ball fine-pitch ball grid array (14 22 1.76 mm) pb-free 100 cy7c1481v33-100axc 51-85050 100-pin thin quad flat pack (14 x 20 x 1.4 mm) pb-free commercial cy7c1483v33-100axc cy7c1481v33-100bzc 51-85165 165-ball fine-pitch ball grid array (15 x 17 x 1.4 mm) cy7c1483v33-100bzc cy7c1481v33-100bzxc 51-85165 165-ball fine-pitch ball grid array (15 x 17 x 1.4 mm) pb-free cy7c1483v33-100bzxc cy7c1487v33-100bgc 51-85167 209-ball fine-pit ch ball grid array (14 22 1.76 mm) cy7c1487v33-100bgxc 209-ball fine-pitch ball grid array (14 22 1.76 mm) pb-free cy7c1481v33-100axi 51-85050 100-pin thin quad flat pack (14 x 20 x 1.4 mm) pb-free lndustrial cy7c1483v33-100axi cy7c1481v33-100bzi 51-85165 165-ball fine-pitch ball grid array (15 x 17 x 1.4 mm) cy7c1483v33-100bzi cy7c1481v33-100bzxi 51-85165 165-ball fine-pitch ball grid array (15 x 17 x 1.4 mm) pb-free cy7c1483v33-100bzxi cy7c1487v33-100bgi 51-85167 209-ball fine-pit ch ball grid array (14 22 1.76 mm) cy7c1487v33-100bgxi 209-ball fine-pitch ball grid array (14 22 1.76 mm) pb-free [+] feedback [+] feedback
cy7c1481v33 cy7c1483v33 cy7c1487v33 document #: 38-05284 rev. *h page 27 of 30 package diagrams figure 5. 100-pin thin plastic quad flatpack (14 x 20 x 1.4 mm), 51-85050 note: 1. jedec std ref ms-026 2. body length dimension does not include mold protrusion/end flash mold protrusion/end flash shall not exceed 0.0098 in (0.25 mm) per side 3. dimensions in millimeters body length dimensions are max plastic body size including mold mismatch 0.300.08 0.65 20.000.10 22.000.20 1.400.05 121 1.60 max. 0.05 min. 0.600.15 0 min. 0.25 0-7 (8x) stand-off r 0.08 min. typ. 0.20 max. 0.15 max. 0.20 max. r 0.08 min. 0.20 max. 14.000.10 16.000.20 0.10 see detail a detail a 1 100 30 0 5 1 3 51 80 81 gauge plane 1.00 ref. 0.20 min. seating plane 51-85050-*b [+] feedback [+] feedback
cy7c1481v33 cy7c1483v33 cy7c1487v33 document #: 38-05284 rev. *h page 28 of 30 figure 6. 165-ball fbga (15 x 17 x 1.4 mm), 51-85165 package diagrams (continued) a 1 pin 1 corner 17.000.10 15.000.10 7.00 1.00 ?0.450.05(165x) ?0.25 m c a b ?0.05 m c b a 0.15(4x) 0.35 1.40 max. seating plane 0.530.05 0.25 c 0.15 c pin 1 corner top view bottom view 2 3 4 5 6 7 8 9 10 10.00 14.00 b c d e f g h j k l m n 11 11 10 9 8 67 5 4 3 2 1 p r p r k m n l j h g f e d c b a c 1.00 5.00 0.36 +0.05 -0.10 51-85165-*a [+] feedback [+] feedback
cy7c1481v33 cy7c1483v33 cy7c1487v33 document #: 38-05284 rev. *h page 29 of 30 ? cypress semiconductor corporation, 2002-2007. the information contained herein is subject to change without notice. cypress s emiconductor corporation assumes no responsibility for the use of any circuitry other than circuitry embodied in a cypress product. nor does it convey or imply any license under patent o r other rights. cypress products are not warranted nor intended to be used for medical, life support, life saving, critical control or safety applications, unless pursuant to an express written agreement with cypress. furthermore, cypress does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to re sult in significant injury to the user. the inclusion of cypress products in life-support systems application implies that the manu facturer assumes all risk of such use and in doing so indemni fies cypress against all charges. i486 is a trademark and intel and pentium are registered trade marks of intel corporation. all products and company names mentioned in this document may be the tr ademarks of their respective holders. figure 7. 209-ball fbga (14 x 22 x 1.76 mm), 51-85167 package diagrams (continued) 51-85167-** [+] feedback [+] feedback
cy7c1481v33 cy7c1483v33 cy7c1487v33 document #: 38-05284 rev. *h page 30 of 30 document history page document title: cy7c1481v33/cy7c1483v 33/cy7c1487v33, 72-mbit (2m x 36/4m x 18/1m x 72) flow-through sram document number: 38-05284 rev. ecn no. issue date orig. of change description of change ** 114671 08/12/02 pks new data sheet *a 118283 01/27/03 hgk updated ordering information updated the features for package offering changed from advance information to preliminary *b 233368 see ecn njy changed timing diagrams changed logic block diagrams modified functional description modified ?functional overview? section added boundary scan order for all packages included thermal numbers and capacitance values for all packages included idd and isb values removed 150-mhz speed grade offering changed package outline for 165fbga package and 209-ball bga package removed 119-bga package offering *c 299452 see ecn syt removed 117-mhz speed bin changed ja from 16.8 to 24.63 c/w and jc from 3.3 to 2.28 c/w for 100 tqfp package on page # 21 added lead-free information for 100-pin tqfp, 165 fbga and 209 bga packages added comment of ?lead-free bg packages availability? below the ordering information *d 323080 see ecn pci address expansion pins/balls in the pinouts for all packages are modified as per jedec standard added address expansion pins in the pin definitions table modified v ol, v oh test conditions removed comment of ?lead-free bg packages availability? below the ordering information updated ordering information table *e 416193 see ecn nxr changed address of cypr ess semiconductor corporation on page# 1 from ?3901 north first street? to ?198 champion court? changed the description of i x from input load current to input leakage current on page# 19 changed the i x current values of mode on page # 19 from -5 a and 30 a to -30 a and 5 a changed the i x current values of zz on page # 19 from -30 a and 5 a to -5 a and 30 a changed v ih < v dd to v ih < v dd on page # 19 replaced package name column with package diagram in the ordering information table *f 470723 see ecn vkn converted from preliminary to final added the maximum rating for supply voltage on v ddq relative to gnd changed t th , t tl from 25 ns to 20 ns and t tdov from 5 ns to 10 ns in tap ac switching characteristics table updated the ordering information table *g 486690 see ecn vkn corrected the typo in the 209-ball fbga pinout. (corrected the ball name h9 to v ss from v ssq ). *h 1062041 see ecn vkn/ kkvtmp added footnote #2 related to v ssq [+] feedback [+] feedback

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